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T2M › DDR › GDDR5X Controller IP

GDDR5X Controller IP

Description

GDDR5X interface provides full support for the GDDR5X interface, compatible with standard JESD232 and JESD232A specification and DFI-version 4.0 or 5.0 Specification Compliant. Through its GDDR5X compatibility, it provides a simple interface to a wide range of low-cost devices. GDDR5X IP is proven in FPGA environment. The host interface of the GDDR5X can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

GDDR5X-Controller-silicon-proven-ip-provider-in-china

 

Features
  • GDDR5X protocol standard JESD232 and JESD232A.
  • Compliant with DFI-version 4.0 or 5.0 Specification.
  • Supports all the GDDR5X commands as per the specs.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi-port arbitration.
  • Supports user programmable page policy. • Closed page policy • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports 4GB, 6GB, 8GB, 12GB, 16GB Package Pin out and Addressing.
  • Supports X16, X32 device modes.
  • Supports for All Mode registers programming.
  • Supports for Bank group features.
  • Supports for Single ended interface for command, address and data.
  • Supports for QDR and DDR operating mode.
  • Supports for Programmable read latency and write latency.
  • Supports for Write data mask function via address bus.
  • Supports for Data bus inversion (DBI) & address bus inversion (ABI).
  • Supports for Input/output PLL/DLL.
  • Supports for Address training.
  • Supports for cyclic redundancy check (CRC-8).
  • Supports for Low Power modes.
  • Supports for Auto & self-refresh modes.
  • Supports for Auto precharge option for each burst access.
  • Supports for On-die termination (ODT) for all highspeed inputs.
  • Supports Mirror function with MF pin.

Deliverables

  • The GDDR5X interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes
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