Description and Features
Ethernet Switch core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of lowcost devices. Ethernet Switch IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

Features
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Compliant with IEEE Standard 802.3-2018 Specification
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Supports Full-duplex and Half-duplex 10M/100M/1G Ethernet interfaces
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Supports 10G/25G/50G/40G and 100G Ethernet interfaces
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Supports MII/GMII/RGMII/QSGMII/USXGMII Physical Layer device (PHY) interfaces
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Supports different data rate for each port
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Supports Dynamic MAC Table with automatic MAC addresses learning and aging
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Supports Static MAC Table
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Supports Jumbo Frame Management
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Supports Ethertype Based Switching
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Supports Ingress Port Mirroring
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Supports Broadcast/Multicast Storm protection
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Supports Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
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Supports timing synchronization as per IEEE Standard 1588-2008(PTP)
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Supports Multicast Frame Filtering
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Supports Switching Portmask
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Supports Port-based VLAN
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Supports QoS - Priorities (PCP-802.1p,DSCP TOS, Ethertype)
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Supports DSA (Distributed Switching Architecture) tagging
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Supports MDIO, AXI4-Lite or CoE(Configuration-over- Ethernet) SOC interfaces
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Supports RSTP (Software stack required)
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Supports MRP (Software stack not required) • Ring Manager (MRM) • Ring Client (MRC)
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Supports DLR (Software stack not required) • Beacon Based Node • Supervisor Node
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In house UNH compliance tested
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices.
Deliverables
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The Ethernet interface is available in Source and netlist products.
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The Source product is delivered in plain textVerilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes