Description
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification. It is compatible with the MIPI Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI protocols). It is a TX PHY with one clock lane and four data lanes. The I/O activities are managed by a digital back end, while electrical level signals are generated and received by an analogue front end. internal termination resistor with auto-calibration. The D- PHY is a MIPI DSI PHY (MIPI TX DPHY) includes a D-PHY that may be used as a GPIO bank with a 5V tolerance, a PLL, a Clock Lane, four Data Lanes, and a clock lane.
Features
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Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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Supports standard PPI interface compliant to MIPI Specification
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Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
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Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
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Supports ultra-low power mode, high speed mode and escape mode
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Supports one clock lane and up to four data lanes
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Data lanes support transfer of data in high speed mode
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Supports error detection mechanism for sequence errors and contentions
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Supports contention detection
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Configurable skew option for each Clock and Data lanes
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Testability for TX, RX and PLL
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Silicon Proven in TSMC 28HPC+
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behaviour model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports
