Description
The SMART is a quick, adaptable, and reasonably priced core designed for smart card reader applications. Based on ISO 7816-3/EMV4.2/4.3 specifications, it offers a communication interface with a smart card. Both T0 character-oriented protocol and T1 block-oriented protocol have hardware support implemented by the SMART IP Core. It was created to combine extremely low CPU usage with little space usage. The SMART can manage resets, handle ATR receiving, activate and deactivate cards, and has a number of other features. The SMART's configuration choices let you customize it to meet your specific requirements and select the proprietary features that are best for the design. Direct Memory Access (DMA) or interrupt-driven data transfer to and from the host system are both possible.
Features
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Compatible with the ISO 7816-3: 2006 and EMV 4.2/4.3 standard
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Support for asynchronous Smart Cards
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Dual configurable length FIFO with two programmable thresholds
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Card detection input
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Software-configurable interrupts
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Automatic convention detection and decoding
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Programmable non-gated card clock generator
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Automatic ETU generator
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DMA support for transmit and receive
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Hardware CRC and LRC calculations
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Card power down mode with clock stop high and clock stop low possibility
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Special fast block mode for T1 protocol (optional)
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CRC/LRC hardware generation and checking
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Byte counter with automatic CRC/LRC affixing (optional)
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No tri-state buffers
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Fully synchronous synthesizable design
Deliverables
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Verilog RTL
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Verification environment
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Testcases
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Synthesis environment/scripts
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User manual
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Verification guide
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Design document
Benefits
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DSMART works with all major CPUs and is 100% compatible with DCD’s MCUs – enabling the same – cryptography.
