USB 3.2 Gen2 PHY IP in 28HPC+

Description

All USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps are supported by the USB 3.2 Gen2X1 transceiver IP. It complies with UTMI+ and PIPE4.0 requirements. The USB 3.2 Gen2X1 IP is backward compatible with high-speed data rates of 480Mbps, full-speed data rates of 12Mbps, and low-speed data rates of 1.5Mbps and has high-speed mixed signal circuits to accommodate Gen2 and Gen1 traffic. In order to support the USB Type-C connector, the USB 3.2 Gen2X1 IP offers an active switch to enable bi-directional plug-in and specific functionality (such as VBUS setup and USB attachment cable orientation recognition) through the CC1/CC2 pins defined in the Type-C connection.

Features

• Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
• Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
• Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
• Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
• Integrates an active switch to support the orientation-less connection with USB Type-C connector
• Provides an auxiliary CC module IP to support USB Type-C related functions
• Supports both wire-bond and flip-chip package type
• Silicon Proven in TSMC 28HPC+

Deliverables

• GDS2 Format and Layer Allocation

• LEF Views for Placement and Routing

• Timing and Power Model Repository in Liberty Format

• Functional Model in Verilog

• Circuit Description with Timing Specifications

• Guidelines and Notes for Layout Design

• Reports on Layout Consistency and Rule Adherence