Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › Memory › DMA Controller with AXI IP

DMA Controller with AXI IP

Description and Features

DMA Controller with AXI interface is full featured, easy-to-use, synthesizable design that can be used with AXI based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between.

DMA-Controller-with-AXI-silicon-proven-ip-provider-in-taiwan

 

Features
  • 1-16 channel DMA Transmit and DMA Receive Engine
  • Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
  • Supports access for Ring and Chained Descriptor Structures
  • Configurable Transmit and Receive Engine based on Host Memory Data Width
  • Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
  • Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width
  • Supports hardware DMA Control registers that can be written and read by CPU
  • Round Robin algorithm for arbitration between DMA Transmit and Receive Engine to access SOC Master Bus
  • SOC Master bus can be AXI/AHB/APB/OCP/Tilelink/Wishbone
  • Supports AXI Slave bus
  • Uses SOC Slave Interface to get Receive and Transmit descriptors and transfer the data to/from the system memory from/to FIFO inside the DMA controller
  • User logic to map data fetched from Host to IP core or from IP core to host
  • Supports Sideband DMA request and Grant based triggering of transfers as on option for peripherals
  • Supports Scatter Gathers list
  • Supports 8/16/32 bit wide data transfers
  • Supports QoS per channel if SOC master interface supports Qos.
  • Supports programmable burst capability per SOC master
  • Supports both single data and burst data transfers, with burst size based on the burst length field in the DMA control registers
  • DMA supports full duplex operation, processing read and write transfers at the same time
  • Supports Link list-based processor for autonomous operation
  • Interface widths can be controller for each SOC master interface
  • Supports per Channel Interrupt output
  • Supports up to 64 MB transfer per Buffer Descriptor (BD

Deliverables

  • The DMA Controller with AXI interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes
Request Datasheet