The eMMC Device Controller IP Core is fullfeatured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eMMC Device Controller IP can be implemented in any technology. The eMMC Device Controller IP core supports the JESD84- B50 specification ad supporting standards. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon, PLB, Tilelink, Wishbone or custom buses. The eMMC Device Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eMMC Device Controller IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
Compliant with JESD84-B50 Specification and earlier versions
Compliant with JEDEC eMMC CQHCI for Command Queuing
Supports different data bus width modes: 1-bit, 4-bit, 8-bit.