Description and Features

The MIPI D-PHY Analog TX IP Core fully complies with the D-PHY specification, version 1.2. It is compatible with both the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) (DSI protocols). This TX PHY consists of one clock lane and four data lanes. Electrical level signals are produced and received by an analogue front end, while I/O activities are managed by a digital back end. internally placed auto-calibrating termination resistor The MIPI DSI PHY consists of the D-PHY, which can be used as a GPIO bank with a 5V tolerance, a PLL, a Clock Lane, four Data Lanes, and a Clock Lane (MIPI TX DPHY).

Features

• Compliant to MIPI Alliance Standard for
• D-PHY specification Version 1.2
• Supports standard PPI interface compliant to MIPI Specification
• Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
• Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
• Supports ultra-low power mode, high speed mode and escape mode
• Supports one clock lane and up to four data lanes
• Data lanes support transfer of data in high speed mode
• Supports error detection mechanism for sequence errors and contentions
• Supports contention detection
• Configurable skew option for each Clock and Data lanes
• Testability for TX, RX and PLL
• Silicon Proven in TSMC 16 FFC.

Deliverables

• GDSII & layer map
• Place-Route views (.LEF)
• Liberty library (.lib)
• Verilog behaviour model
• Netlist & SDF timing
• Layout guidelines, application notes
• LVS/DRC verification reports