MIPI D-PHY Tx IP in 16FFC

Description

The MIPI D-PHY Tx IP Core is fully compliant with the D-PHY specification, version 1.2, ensuring adherence to industry standards. It offers compatibility with both the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) protocols, enhancing versatility in integration. Featuring one clock lane and four data lanes, this TX PHY provides robust connectivity solutions.

Electrical level signals are meticulously handled by the analog front end, ensuring reliable signal transmission and reception. Meanwhile, the digital back end efficiently manages I/O operations, optimizing performance and functionality. Additionally, the core includes an internally placed auto-calibrating termination resistor, enhancing signal integrity and stability.

Furthermore, the MIPI DSI PHY encompasses essential components such as the D-PHY, which serves as a GPIO bank with a 5V tolerance, along with a PLL, Clock Lane, four Data Lanes, and a Clock Lane (MIPI TX DPHY). This comprehensive setup enables seamless integration and operation within diverse system architectures.

Features

• Compliant to MIPI Alliance Standard for
• D-PHY specification Version 1.2
• Supports standard PPI interface compliant to MIPI Specification
• Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
• Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
• Supports ultra-low power mode, high speed mode and escape mode
• Supports one clock lane and up to four data lanes
• Data lanes support transfer of data in high speed mode
• Supports error detection mechanism for sequence errors and contentions
• Supports contention detection
• Configurable skew option for each Clock and Data lanes
• Testability for TX, RX and PLL
• Silicon Proven in TSMC 16 FFC.

Deliverables

• GDSII & layer map
• Place-Route views (.LEF)
• Liberty library (.lib)
• Verilog behaviour model
• Netlist & SDF timing
• Layout guidelines, application notes
• LVS/DRC verification reports