SDR PHY for 4G/5G and large MIMO system

Description

This SDR is a development platform for realization networks like 4G/5G and other radio applications involving more than 4 or 8 antenna ports. The SDR platforms have the mix of practical deployment scenarios and high-performance computing platforms to scale the simulations to RF. The Jupiter HW uses TCI6638K2K System on Chip (SoC) from Texas Instrument. The SoC brings in enormous computing power to develop PHY and Higher Layer Software.

The platform can be used for building application with 4x4 MIMO and channel BW exceeding 60 MHz.

The platform’s capabilities are demonstrated using LTE eNB and UE application. The platform is supplied with example application to transmit and receive IQ sample vectors.

Development Environment -

• The DSPs on the SOC is programmed using the Code Composer Studio, IDE from Texas Instruments.
• The ARM Cortex A15 cores are programmed with the help of GCC compilers
• FPGA code is developed using Vivado Tools from Xlinx

Features

• 8x8 Transmit and Receive Antennas support
• TI Multi-core communication processor, 1.2 GHz
• 8 C66X DSP cores and 4 ARM cores
• NOR flash – 32MB, NAND Flash – 512MB
• HW accelerator blocks like FFT, FEC (Viterbi and Turbo), Packet Processing and Security Acceleration.
• FMC, HPC and LLC Header for the interface to AD9361 boards.
• Radio front end for LTE TDD/FDD band
• Power Amplifier, LNA and Duplexer for Band 7