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T2M › Ethernet › Ethernet 1G MAC IP

Ethernet 1G MAC IP

Description and Features

The Ethernet 1G MAC IP Core is fullfeatured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 1G MAC IP can be implemented in any technology. The Ethernet 1G MAC IP core supports the Ethernet protocol standard of IEEE 802.3.2018 specification. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The Ethernet 1G MAC IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 1G MAC IP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

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Features
  • Compliant with IEEE Standard 802.3.2018 specification
  • Support for Full duplex and Half duplex mode
  • Supports GMII and MII Interfaces
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Supports Programmable Inter Packed Gap(IPG) and Preamble length
  • Provides detailed statistics as per the specification
  • Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
  • Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
  • Supports Wake-on-LAN
  • Supports Loopback Functionality
  • Supports Control frame and Jumbo frame
  • Supports transmit and receive FIFO interface
  • Supports FCS (CRC) transmission and reception
  • Supports Pause frame based flow control in full duplex mode
  • Supports AXI stream Interface for System Interface
  • In house UNH compliance tested
  • Optional support for TCP/IP
  • Optional support for IEEE Standard 1588-2008 PTP
  • Optional support for DMA support for both transmit and receive side
  • Optional support for RMII, RGMII and TBI interfaces
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Deliverables

  • RTL design in Verilog
  • Lint, CDC, Synthesis Script with waiver files
  • Lint, CDC, Synthesis Reports
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Technical documentation in greater detail
  • Easy to use Verilog Test Environment with Verilog Test cases

Benefits

  • Fully compliant, silicon-proven core
  • Comes with Verilog testbench and option to buy full advanced System Testbench
  • Support directly from engineer who designed the code
  • Based on RMM (Re Use Methodology Manual guidelines)
  • Supports all the Synthesis tools
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