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T2M MIPI MIPI D-PHY Tx IP in 22ULP

MIPI D-PHY Tx IP in 22ULP

Description and Features

The MIPI D-PHY Analog TX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI protocols). It is a TX PHY with one clock lane and 4 data lanes. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. Internal termination resistor with auto-calibration- PHY is a MIPI DSI PHY (MIPI TX DPHY) Includes a PLL, a Clock Lane and four Data Lane for MIPI DSI data transmission, also D-PHY can be used as a 5V tolerance GPIO bank.

 

Features

DSI PCS :

  • The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.

  • Host_adapter: remapping PPI Signal with lane control and phy_adapter block;

  • Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)

  • acknowledges the operation on PPI interface. It enables a high-speed transmission or low-power transmission/reception and schedules the activities inside the link.

  • PHY_adapter: remappig lane_ctrl Signal with phy interface;

DSI PMA:

  • A PLL for high speed clock and MIPI data clock generation
  • Data MUX and Reference resistor calibration
  • MIPI PHY IO with GPIO compatible
  • Silicon Proven in

Deliverables

  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behaviour model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports