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MIPI D-PHY Tx IP in 28HPC+

Description and Features

The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification. It supports the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) protocols. Operating as a Tx PHY, it consists of one clock lane and four data lanes. The digital backend manages I/O operations, while the analog frontend generates and receives electrical signals. Additionally, it features an auto-calibrating internal termination resistor. This MIPI DSI PHY encompasses a MIPI D-PHY Tx IP Core incorporating a PLL, a Clock Lane, four Data Lanes, and the option to utilize the D-PHY as a GPIO bank with a 5V tolerance.

Features
  • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
  • Supports ultra-low power mode, high speed mode and escape mode
  • Supports one clock lane and up to four data lanes
  • Data lanes support transfer of data in high speed mode
  • Supports error detection mechanism for sequence errors and contentions
  • Supports contention detection
  • Configurable skew option for each Clock and Data lanes
  • Testability for TX, RX and PLL
  • Silicon Proven in TSMC 28HPC+

Deliverables

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports
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