This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification. The Gen 3 has a capability for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Furthermore, because the low power mode option is customizable, the PHY is extensively relevant for a variety of situations with varying power consumption considerations.
T2M provides the best-in-class, highly configurable PCIe 3.0 PHY that complies with ECN 1.0a and PCie 3.0 specifications and is aimed at both client and corporate applications. The eight-lane arrangement of the PHY IP allows for maximum throughput while supporting a wide range of applications. It can be tailored by the client for lower data rates (Gen2) or fewer lanes. Additionally, it offers L1 substates L1.1 and L1.2, allowing for easy integration in applications with strict power requirements while maintaining minimal silicon area.
Silicon Proven in GF 22GDX with 0.8V and 1.8V power supply.
Compatible with PCIe base Specification
Support 32-bit/16-bit parallel interface
Support for PCIe3(8.0Gbps)
Backward compatible with 2.5Gbps and 5Gbps for
Full compatible with PIPE4.2 interface specification
Support 100MHz differential reference clock input/output (with SSC optionally)
ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
Support programmable transmit amplitude and Deemphasis, Pre-shoot
Support Beacon signal generation and detection
Production test support is optimized through high coverage at-speed BIST and loopback
Integrated on-die termination resistors and IO Pads/Bumps
Embedded Primary & Secondary ESD Protection
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
