Description and Features
Ethernet 400G MAC core is compliant with IEEE Standard 802.3.2018 and IEEE 802.3bs Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of lowcost devices. Ethernet 400G MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

Features
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Compliant with IEEE Standard 802.3-2018 specification and IEEE 802.3bs specification.
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Supports full duplex mode of operation
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Supports standard 400Gbps Ethernet link layer data
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Supports CDMII (Clause 116) interface.
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Supports 64bit Transmit and Receive Path
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Supports Programmable Inter Packet Gap and Preamble length
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Supports MDIO (Clause 22 and Clause 45) Interface
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Supports start control character alignment
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Provides detailed statistics as per specification
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Supports Jumbo Frame
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Supports Loopback functionality
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Supports transmit and receive FIFO interface
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Supports FCS(CRC) transmission and reception
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Supports Pause frame-based flow control
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Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
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Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
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Supports Wake-on-LAN
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In house UNH compliance tested
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Optional support for TCP/IP
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Optional support for IEEE Standard 1588-2008 PTP
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Optional support for DMA support for both transmits and receive side
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Benefits
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Single Site license option is provided to companies designing in a single site.
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Multi Sites license option is provided to companies designing in multiple sites.
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Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC
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Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
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The Ethernet interface is available in Source and netlist products.
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The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes