Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.1 Type-C PHY IP in 12SF++

USB 3.1 Type-C PHY IP in 12SF++

Description and Features

A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data transfers while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A separate PCS can be provided in addition to the USB 3.1 Type C PHY IP to complete the functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing. Depending on the customer's request, PCS is offered as either a hard macro or a soft macro. The PCS standard will also be made accessible independently. A test bench created in Verilog HDL is used to validate PHY functionality by the NC-Verilog simulation program.


  • Support half rate mode (5Gbps) and full rate mode (10Gbps)
  • Tolerate max +/-7000ppm input frequency offset
  • 32bit/40bit selectable parallel data bus
  • Programmable transmit amplitude
  • 3 taps/2 taps selectable FFE
  • Receiver CTLE and One-tap perspective DFE
  • Build in self-test with PRBS7/31 pattern generation and checker for production test
  • Integrated on-die termination resistors
  • Support receiver detection
  • Support LFPS signal generation and detection
  • Support Spread Spectrum clock generation and receiving
  • Flexible reference clock frequency
  • Do not need any external component
  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
  • Metal Layer:M1~M7+RDL
  • Core Voltage: 1.1V
  • IO Voltage: 3.3V
  • Silicon Proven in SMIC 12SF++


  • Graphic Data System II File with Layer Configuration .

  • LEF Files Containing Placement and Routing Views

  • Standard Cell Library with Timing and Power Models

  • Verilog Representation of Functional Behavior

  • Netlist Annotated with Standard Delay Format Timing Constraints

  • Application Notes Offering Layout Guidelines

  • LVS and DRC Verification Results Documentation