Description and Features
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data transfers while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A separate PCS can be provided in addition to the USB 3.1 Type C PHY IP to complete the functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing. Depending on the customer's request, PCS is offered as either a hard macro or a soft macro. The PCS standard will also be made accessible independently. A test bench created in Verilog HDL is used to validate PHY functionality by the NC-Verilog simulation program.

Features
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Support half rate mode (5Gbps) and full rate mode (10Gbps)
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Tolerate max +/-7000ppm input frequency offset
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32bit/40bit selectable parallel data bus
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Programmable transmit amplitude
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3 taps/2 taps selectable FFE
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Receiver CTLE and One-tap perspective DFE
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Build in self-test with PRBS7/31 pattern generation and checker for production test
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Integrated on-die termination resistors
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Support receiver detection
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Support LFPS signal generation and detection
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Support Spread Spectrum clock generation and receiving
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Flexible reference clock frequency
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Do not need any external component
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ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
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Metal Layer:M1~M7+RDL
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Core Voltage: 1.1V
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IO Voltage: 3.3V
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Silicon Proven in SMIC 12SF++
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behavior model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports
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Test patterns and Test Documentation