Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M DisplayPort eDisplay Port v1.4 Rx PHY IP in 40LL

eDisplay Port v1.4 Rx PHY IP in 40LL

Description and Features

The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-gigabit receiver macro compliant with eDP standards. This adaptable and dependable solution enables data reception speeds reaching 5.4Gbps, optimizing both power usage and die size. It boasts simplicity in production and integration into Video Interface systems. The AUX channel supports a bit rate close to 1Mbps, functioning as a half-duplex, bidirectional channel composed of a single differential pair. Each macro includes an AUX channel with one PLL and bias gen unit, along with multiple receiver channels. Essential functions of the receiver encompass a dedicated equalizer, clock and data recovery (CDR), S2P, and self-test features, with the ability to disable individual channels as needed.


  • Low power operation: 22mW/lane @ typical

  • Support data rate: 0.6Gbps~5.4Gbps

  • Utilize 10bit parallel interface for per lane

  • Independent power down control for each lane

  • Implemented CTLE to compensate channel loss

  • Integrated on-die termination resistors

  • Tolerance maximum SSC ±15000ppm@30KHz

  • AC coupling

  • Support 4X, 8X, 16X channel configuration

  • One independent PLL is shared in every macro

  • Support PRBS loopback in every channel

  • AUX channel included

  • Support BGA, QFN/QFP package

  • Metal option: 1P8M-7lc-1TMc-ALPA1

  • Silicon Proven in SMIC 40LL


  • Application Note / User Manual

  • Behaviour model, and protected RTL codes

  • Protected Post layout netlist and Standard

  • Delay Format (SDF)

  • Frame view (LEF)

  • Metal GDS (GDSII)

  • Test patterns and Test Documentation