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T2M DisplayPort eDisplay Port v1.4 Rx PHY IP in 40LL

eDisplay Port v1.4 Rx PHY IP in 40LL

Description and Features

eDisplay Port v1.4 RX-PHY is made for chips that can communicate data at high bandwidth while using little power. It is a multi-gigabit receiver macro that conforms with eDP. This versatile and reliable solution allows for data reception speeds of up to 5.4Gbps with optimum power and die size. It is also, simple to produce and implement in Video Interface The AUX channel supports a bit rate of approximately 1Mbps and is a half-duplex, the bidirectional channel made up of one differential pair. Each macro has an AUX channel with one PLL and bias gen unit as well as many receiver channels. A dedicated equalizer, clock and data recovery (CDR), S2P, and self-test are all functions of the receiver. Channels can all be individually disabled.


  • Low power operation: 22mW/lane @ typical

  • Support data rate: 0.6Gbps~5.4Gbps

  • Utilize 10bit parallel interface for per lane

  • Independent power down control for each lane

  • Implemented CTLE to compensate channel loss

  • Integrated on-die termination resistors

  • Tolerance maximum SSC ±15000ppm@30KHz

  • AC coupling

  • Support 4X, 8X, 16X channel configuration

  • One independent PLL is shared in every macro

  • Support PRBS loopback in every channel

  • AUX channel included

  • Support BGA, QFN/QFP package

  • Metal option: 1P8M-7lc-1TMc-ALPA1

  • Silicon Proven in SMIC 40LL


  • Application Note / User Manual

  • Behaviour model, and protected RTL codes

  • Protected Post layout netlist and Standard

  • Delay Format (SDF)

  • Frame view (LEF)

  • Metal GDS (GDSII)

  • Test patterns and Test Documentation