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Semiconductor IP Cores

T2M › Ethernet › Ethernet 25G MAC IP

Ethernet 25G MAC IP

Description

Ethernet 25G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 25G MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

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Features
  • Compliant with IEEE Standard 802.3-2018 specification
  • Supports full duplex mode of operation
  • Supports Standard 25Gbps Ethernet link layer data
  • Supports 25GMII (Clause 106) interface operating at 390.625MHz
  • Supports Programmable Inter Packet Gap (IPG) and Preamble length
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Supports start control character alignment
  • Provides detailed statistics as per the specification
  • Supports Jumbo Frame
  • Supports Loopback functionality
  • Supports transmit and receive FIFO interface
  • Supports FCS(CRC) transmission and reception
  • Supports Pause frame-based flow control
  • Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
  • Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
  • Optional Wake-on-LAN support
  • Supports AXI stream Interface for System Interface
  • In house UNH compliance tested
  • Optional support for TCP/IP offload
  • Optional support for IEEE Standard 1588-2008 PTP
  • Optional support for DMA on both transmits and receive side
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

  • The Ethernet interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes
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