IEEE 1588 core is compliant with IEEE Standard 1588- 2019 specification. Through its compatibility, it provides a simple interface to a wide range of lowcost devices. IEEE 1588 IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXILite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses IEEE 1588 IIP is supported natively in Verilog and VHDL
Compliant with IEEE Standard 1588-2019 specification
Supports for TSN required PTP as per IEEE 802.1AS
Configurable as PTP Master or PTP Slave
Supports both end to end and peer to peer delay mechanism
Generates timestamp based on Real time clock (high precision clock)
Generates Follow up message if it is a 2 step delay mechanism (when configured as Master)
Generates Delay Response message on reception of Delay Request message (when configured as Master)
Configurable for Delay Mechanism (End to end or peer to peer)
Formal mechanisms for message extensions (using TLV)
Transparent clocks
Options for redundancy and fault tolerance
New management capabilities and options
Optional unicast messaging (in addition to multicast)
Tight integration with SmartDV Ethernet MAC of all speeds
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to Microprocessor/Microcontroller devices
Deliverables
The IEEE 1588 interface is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.
