Ethernet 40G MAC IP

Description

Ethernet 40G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 40G MAC IP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses

Features

• Compliant with IEEE Standard 802.3-2018 specification
• Supports full duplex mode operation
• Supports XLGMII (Clause 81) interface
• Supports Programmable Inter Packet Gap (IPG) and Preamble length
• Supports MDIO (Clause 22 and Clause 45) Interface
• Supports start control character alignment
• Provides detailed statistics as per the specification
• Supports Loopback functionality
• Supports Control frame and Jumbo Frame
• Supports transmit and receive FIFO interface
• Supports FCS(CRC) transmission and reception
• Supports Pause frame-based flow control
• Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
• Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
• Supports Wake-on-LAN support
• Supports AXI stream Interface for System Interface
• In house UNH compliance tested
• Optional support for TCP/IP
• Optional support for IEEE Standard 1588-2008 PTP
• Optional DMA support for both transmit and receive side
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• A specialized license for companies with operations confined to a single site, offering streamlined access.

• A flexible licensing option for companies spanning multiple sites, providing adaptable usage.

• Allows integration of the IP Core into a sole FPGA bitstream and ASIC, ensuring focused deployment.

• Grants limitless usage of the IP Core across diverse FPGA bitstreams and ASIC designs, promoting unrestricted creativity and scalability.

Deliverables

• Implementing Verilog RTL design

• Validation scripts covering Linting, CDC analysis, and Synthesis, with waivers integrated

• Detailed reports providing insights into Linting, CDC analysis, and Synthesis methodologies

• Utilizing IP-XACT RDL to generate an address map

• Consolidating firmware code and Linux drivers into a single package

• Thorough technical documentation comprehensively covering all aspects

• Verilog Test Environment with seamlessly integrated intuitive test cases