Description
MPEG4 Decoder core is compliant with MPEG-4 standard specification. Through its compatibility, it provides a simple interface to a wide range of lowcost devices MPEG4 Decoder is proven in FPGA environment. The host interface of the MPEG4 can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Features
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Supports MPEG-4 standard specification.
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Supports full MPEG-4 decoder functionality.
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Supports YUV 4:2:2 interleaved data as an input
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Supports image width as multiple of 16 and height as multiple of 16
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Supports Half Pel Interpolation (HPI) for motion estimation
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Supports generation of streams with resync marker (RM)
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Supports Unrestricted Motion Vectors (UMV)
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Supports video resolution up to 1920x1080@60fps.
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Supports Chroma type 4:4:4, 4:2:2 and 4:2:0.
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Benefits
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Single site license option is provided to companies designing in a single site.
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Multi sites license option is provided to companies designing in multiple sites.
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Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
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Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
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The MPEG4 Decoder interface is available in Source and netlist products.
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The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.
