For peripheral devices, there is a Universal Serial Bus (USB) transceiver available. The USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI standards are all met by the PHY. The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip, without compromising speed or data throughput. A complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalisation circuit are all included in the USB3.0 PHY IP to assure full support for high-performance designs. Multiple IP sources are supported for the USB3 MAC layer through the standard PHY interface (PIPE). Internal test control and permissible parameter tweaking for analogue circuits with integrated Jitter Injection Output and Built-in Self-Test Jitter minimization by the use of consistent power.
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Deliverables
IC Layout Representation with Layer Mapping in GDSII
Layout Exchange Format Files for Placement and Routing Visualization
Liberty Format Library for Timing and Power Characterization
Verilog Model for Functional Simulation
Circuit Description with Timing Specifications in SDF Format
Guidelines and Insights for Effective Layout Design
Verification Reports Confirming Layout Schematic and Rule Adherence
