Description and Features
MIPI CSI-3 is a new generation of camera serial interface, expanding on the capabilities of CSI-2. By using a multipurpose link based on a common protocol stack (UniPort-M), CSI-3 provides higher bandwidth over fewer pins, with better power per bit efficiency than CSI-2. The MIPI CSI-3 Verification IP is fully compliant with version 1.2 MIPI Alliance specification for camera serial Interface 3 and provides the following features. MIPI CSI-3 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and nonstandard verification env MIPI CSI-3 Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.

Features
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Supports Version 1.2 MIPI CSI-3 Specification
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Supports transmission of Image frame
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Supports transmission of Attribute packets
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Supports Data transmission on multiple Virtual Channels
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CAL provides support for camera configuration, camera control and data transport
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Includes Proven MIPI UniPro and M-PHY bfm components for lower layer verification
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M-PHY supports various transmission speed steps and ranges from 0.01 Mbps up to 5.8 Gbps per Lane
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Supports all lane configuration
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Supports implementation of standalone ISPs
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Supports interleave the streams
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Supports all CSI-2 legacy data formats
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Supports following error insertion and detection
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All MIPI MPHY errors, Disparity errors, Invalid code group errors, All Unipro errors, Invalid frame formats, L2 Credit violation, Cport buffer violation
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All LSS errors, No response error injection
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CRC errors, Reserve field error injection
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Over and undersize errors, Lane mapping and disconnection error, All CSI-3 erros, Data type errors
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Over and undersize errors, Malformed packet errors
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Attribute errors
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Supports compressed image data
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The CCI device supports all four different read operations • Single read from random location • Sequential read from random location • Single read from current location • Sequential read from current location
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The CCI device supports all two different write operations • Single write to random location • Sequential write starting from random location
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The CCI supports the following register width
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8-bit, 16 bit, 32 bit, 64 bit
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Monitor, Detects and notifies the testbench of all protocol and timing errors
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Supports constraints Randomization
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Status counters for various events in bus
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Callbacks in transmitter and receiver for various events
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MIPI CSI-3 Verification IP comes with complete test suite to test every feature of MIPI CSI-3 Version 1.0 specification.
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Functional coverage for complete MIPI CSI-3 features
Deliverables
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Complete regression suite containing all the MIPI CSI-3 testcases.
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Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes