A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fundamental specifications while integrating mixed signal circuits to provide 2.5GT/s and 5.0GT/s data transfer speeds. Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS) are the two levels that make up the PCIe2.0 PHY IP. It simply connects to either the PCIe2.0 MAC layer utilizing the industrystandard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.
Compatible with PCIe base Specification
Full compatible with PIPE4.2 interface specification
Independent channel power down control
Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
Support 16-bit/32bit parallel interface
Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
Support flexible reference clock frequency
Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
Support programmable transmit amplitude and Deemphasis
Support TX detect RX function in PCIe Mode
Support Beacon signal generation and detection in
Production test support is optimized through high coverage at-speed BIST and loopback
Integrated on-die termination resistors and IO Pads/Bumps
Embedded Primary & Secondary ESD Protection
ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
Silicon Proven in SMIC 28HKMG
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
