Description
MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI SPMI Slave IP is proven in FPGA environment.The host interface of the MIPI SPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Features
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Supports 2.0 and 1.0 MIPI SPMI Specification
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Full MIPI SPMI Slave functionality
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Supports following frames • Command Frame • Data/Address Frame • No Response Frame
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Supports ACK/NACK as per 2.0 specs
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Support for slave requests through Alert(A) / Slave Request (SR) bit.
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Support for slave request hold.
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Glitch suppression (optional).
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Supports extended register read/writes
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Supports wakeup command
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Supports Authentication Command Sequence
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Device Descriptor Block Command Sequences
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to microprocessor/microcontroller devices.
Benefits
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Single Site license option is provided to companies designing in a single site.
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Multi Sites license option is provided to companies designing in multiple sites.
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Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
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Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
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The MIPI SPMI Slave interface is available in Source and netlist products.
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The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.