Ethernet 40/100G TSN MAC core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet TSN IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 40/100G TSN MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Benefits
Customized licensing option catering to companies stationed at a single site, ensuring focused utilization.
Flexible licensing solution accommodating companies with operations spread across multiple sites, facilitating widespread adoption.
Grants permission to integrate the IP Core into a single FPGA bitstream and ASIC, enabling targeted implementation.
Provides unrestricted access to the IP Core for integration into an unlimited number of FPGA bitstreams and ASIC designs, fostering boundless creativity and scalability.
Deliverables
Implementation of Verilog RTL design in action
Validation scripts covering Linting, CDC analysis, and Synthesis, seamlessly integrating waivers
Detailed and elaborate reports offering comprehensive insights into Linting, CDC analysis, and Synthesis methodologies
Leveraging IP-XACT RDL for effective address map generation
Merging firmware code and Linux drivers into a consolidated package
Thorough and exhaustive technical documentation comprehensively addressing all aspects
Verilog Test Environment featuring seamlessly integrated and intuitive test cases
