A Universal Serial Bus (USB) transceiver is available for auxiliary devices. The PHY meets with the specifications of USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI. Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. To offer complete support for high-performance designs, the USB3.0 PHY IP comprises a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalization circuit. The USB3 MAC layer supports several IP sources across the common PHY interface (PIPE). Utilizing constant power, inbuilt Jitter Injection Output, built-in Self-Test, and authorized changing of analogue circuit characteristics, internal test monitoring and jitter is minimized.
Deliverables
GDSII File with Layer Mapping Details .
LEF Files Containing Placement and Routing Views .
lib File with Timing, Power, and Noise Models
Verilog Model for Functional Simulation
Netlist with SDF Timing Annotations
Application Notes for Layout Guidelines
Verification Reports for LVS and DRC Checks
