Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


USB 3.0 PHY IP in 7FF

Description and Features

A Universal Serial Bus (USB) transceiver is available for auxiliary devices. The PHY meets with the specifications of USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI. Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. To offer complete support for high-performance designs, the USB3.0 PHY IP comprises a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalization circuit. The USB3 MAC layer supports several IP sources across the common PHY interface (PIPE). Utilizing constant power, inbuilt Jitter Injection Output, built-in Self-Test, and authorized changing of analogue circuit characteristics, internal test monitoring and jitter is minimized.


  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in TSMC 7FF.


  • GDSII File with Layer Mapping Details .

  • LEF Files Containing Placement and Routing Views .

  • lib File with Timing, Power, and Noise Models

  • Verilog Model for Functional Simulation

  • Netlist with SDF Timing Annotations

  • Application Notes for Layout Guidelines

  • Verification Reports for LVS and DRC Checks