The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a transmitter and receiver are defined by the V-by-One HS Standard. This supports up to 4Gbps/lane and has available 8-lane and 16-lane PHY for Tx and Rx.
Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
DC coupling mode
Multi-channel shared offset
Built-in terminal impedance circuit, without external components
Support AXI stream bus protocol and data transceiver
Built-in self-test mechanism, which can independently complete feature and mass production testing
Support link training mode
Support Flip-chip package form
ESD: HBM/MM/CDM/Latch-Up 2000V /200V/ 500V/100mA.
Silicon Proven in SMIC 40LL.
Deliverables
Datasheet
Integration guideline
GDSII or Phantom
GDSII Layer map table
CDL netlist for LVS
LEF Verilog behavior model
Liberty timing model DRC/LVS/ERC results
