The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2. The Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2) protocols can be utilized. Four data lanes and one clock lane make up this RX PHY's configuration. The D-PHY consists of a digital back end for controlling I/O operations and an analogue front end for producing and receiving electrical level signals. The intrinsic resistor is automatically terminated.
Compliant to MIPI Alliance Standard for
D-PHY specification Version 1.2
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Supports ultra-low power mode, high-speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high-speed mode
Supports error detection mechanism for sequence errors and contentions
Supports contention detection
Configurable skew option for each Clock and Data lanes
Silicon Proven in UMC 55 LP.
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
