The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification. It is compatible with the MIPI Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI protocols). It is a TX PHY with one clock lane and four data lanes. The I/O activities are managed by a digital back end, while electrical level signals are generated and received by an analogue front end. internal termination resistor with auto-calibration The D- PHY is a MIPI DSI PHY (MIPI TX DPHY) that includes a D-PHY that may be used as a GPIO bank with a 5V tolerance, a PLL, a Clock Lane, four Data Lanes, and a clock lane.
Compliant to MIPI Alliance Standard for
D-PHY specification Version 1.2
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Supports ultra-low power mode, high-speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high-speed mode
Supports error detection mechanism for sequence errors and contentions
Supports contention detection
Configurable skew option for each Clock and Data lanes
Testability for TX, RX and PLL
Silicon Proven in SMIC 55LL
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
