Description
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DVD player/recorders and camcorders, the HDMI transmitter PHY offers an easyto-implement system LSI solution that supports pixel clocks between 25MHz and 250MHz. The following Fab/Nodes have all undergone Silicon Proving: (TSMC, UMC, SMIC, GF, Samsung, ST). It will be straightforward to integrate the HDMI Transmitter Link IP Core into the SoC of consumer goods because it supports HDMI 1.4b and runs at 2.25 Gbps, 16-bit deep colour, and 3D compatibility (HD-TV, AV receiver... etc.). When used in conjunction with the HDMI Transmitter PHY IP, the HDMI Rx IP will perform to the very best of its ability in terms of performance, value, and efficiency. Various HDMI Tx IP configurations are available.
Features
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HDMI version 1.4 compliant transmitter
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Supports DTV from 480i to 1080i/p HD resolution
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Supports 24bit, 30bit and 36bit color depth per pixel
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Integrated cable terminator
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Adaptive equalizer for cable
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Adjustable analog characteristics
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PLL band width
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VCO gain
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BGR voltage
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Cable terminator resistance value
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DLL digital filter characteristics
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Integrated Audio PLL
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3.3V/2.5V/1.0V power supply
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HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
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Controller Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
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Supports 3D video format specified in HDMI 1.4a specification
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Programmable 2-way color space converter
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Compliant with EIA/CEA-861D
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Deep color supported up to 16bit per pixel
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xvYCC Enhanced Colorimetry
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All packet reception including Gamut Metadata Packet
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Supports RGB, YCbCr digital video output format including ITU.656
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24/30/36/48bit RGB/YCbCr 4:4:4
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16/20/24bit YCbCr 4:2:2
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8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
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48 bit mode is not supported in 1080p
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Supports standard SPDIF output for stereo or compressed audio up to 192KHz
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Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
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IEC60958 or IEC61937 compatible
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1bit audio format (Super Audio CD) output
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High-bitrate compressed audio formats output
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Slave I2C interface for DDC connection
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Configuration registers programmable via synchronized parallel interface
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Interface to external HDCP key storage
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Silicon Proven in GF 65/55LPe.
Deliverables
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GDS
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Configurable RTL Code
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HDL based test bench and behavioral models
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Test cases
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Protocol checkers, bus watchers and performance monitors
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Configurable synthesis shell
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Documentation
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Design Guide
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Verification Guide
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Synthesis Guide
