Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M Analog/Codec 500MHz integer-N PLL IP Core

500MHz integer-N PLL IP Core

Description and Features

A programmable on-the-fly Fractional-N PLL at 500MHz is required to lock to an incoming clock source and produce an output clock available at 22nm.


  • Integer Division
  • High Stability
  • Designed to be power-efficient
  • Low Jitter
  • Programmable Loop Filter
  • Lock Detection
  • Small Footprint designed to be compact    


  • LVS Spice netlist
  • Verilog model
  • LEF for clock generator
  • PLL
  • User Guidelines including:
  •   integration guidelines
  •   layout guidelines
  •   testability guidelines
  •   packaging guidelines
  •   board-level guidelines