Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M DisplayPort Display Port v2.0 Rx Controller IP

Display Port v2.0 Rx Controller IP

Description and Features

Display Port Rx Controller core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DISPLAY PORT v2.0 Rx CONTROLLER IP is proven in FPGA environment. The host interface of the Display Port can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.



  • Compliant with Display Port version 2.0 specification.
  • Supports full Display port Receiver functionality
  • Supports multi lanes upto 4 lanes
  • Supports 10bit, 20bit, 40bit, and 80bit parallelinterfaces
  • Supports 1/4/8/16 pixels per clock
  • Supports control symbols for framing (Both Default & Enhanced framing mode)
  • Supports interlaced & non-interlaced video stream
  • Supports backwards compatibility
  • Supports nibble interleaving (ECC)
  • Supports main link, Aux link and Hot plugfunctionality
  • Supports fast link training
  • Supports full link training
  • Supports skip the link training
  • Supports I2C over AUX CH and EDID
  • Supports symbol Stuffing and Transfer Unit
  • Supports 3D stereo and Panel Replay
  • Supports ANSI10B8B decoding.
  • Supports 132b/128b channel decoding.
  • Supports all the video formats which are mentioned in Display Port upto 2.0 version
  • Supports all secondary packet formats which are mentioned in Display Port upto 2.0 version.
  • Supports HPD based link training
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420, YOnly and RAW color format
  • Supports Split SDP for both SST and MST mode
  • Supports all audio formats which are mentioned inIEC 60958-1, IEC 60958-3, IEC 60958-4, IEC 61937-1,IEC 61937-3, CEA/CTA 861-F, 861-G
  • Supports training pattern sequence (TPS2, TPS3,TPS4)
  • Supports descrambler as in Display portspecification
  • Descrambler can be enabled or disabled dynamically
  • Supports descrambler reset after every 512thsymbol
  • Supports Multi Stream Transport (MST) operation
  • Supports Advanced Link Power Management to reduce wake latency
  • Supports GTC-based video timing synchronization
  • Supports Display Stream De-Compression (DSC) up to version 1.2a
  • Supports Horizontal Blanking Expansion
  • Supports RBR, HBR, HBR2, HBR3 and Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates


  • The Display Port Receiver interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.