Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › DisplayPort › DisplayPort v2.0 Rx Controller IP

DisplayPort v2.0 Rx Controller IP

Description

This DisplayPort v2.0 Rx Controller IP Core is designed to be fully compliant with DisplayPort version 2.0 specifications and designers can build VESA-compliant products. Its compatibility ensures seamless integration with a wide range of affordable devices. The DISPLAY PORT v2.0 Rx CONTROLLER IP Core has been thoroughly tested and proven in ASIC/FPGA environments, ensuring its reliability and performance. DisplayPort host interface options can be customized to meet specific requirements, including simple interfaces or popular protocols such as AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or even custom protocols. This flexibility enables easy integration in different system architectures ensuring optimal functionality and interoperability. The DisplayPort v2.0 Rx Controller IP core is a state-of-the-art solution that enables efficient video and audio reception in electronic devices. It supports the DisplayPort v2.0 Controller IP Core standard and offers improved transfer rates of up to 20 Gbps per lane. It supports resolutions up to 8K 60 Hz or 4K 240 Hz, so it offers excellent image quality. The IP core also features multi-stream transport for easy configuration of multi-screen settings, HDR support for real images, and forward error correction for reliable data transmission. HDCP 2.3 support and low power consumption make it the perfect choice for next-generation display systems.

 

 

 

Features
  • Compliant with DisplayPort version 2.0 specification.
  • Supports full DisplayPort Receiver functionality.
  • Supports multi lanes up to 4 lanes.
  • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces.
  • Supports 1/4/8/16 pixels per clock.
  • Supports control symbols for framing (Both Default & Enhanced framing mode)
  • Supports interlaced & non-interlaced video streams.
  • Supports backward compatibility.
  • Supports nibble interleaving (ECC)
  • Supports main link, Aux link and Hot plug functionality
  • Supports fast link training.
  • Supports full link training.
  • Supports skip-the-link training.
  • Supports I2C over AUX CH and EDID
  • Supports symbol Stuffing and Transfer Unit
  • Supports 3D stereo.
  • Supports ANSI10B8B decoding.
  • Supports 132b/128b channel decoding.
  • Supports all the video formats which are mentioned in DisplayPort up to 2.0 version.
  • Supports all secondary packet formats which are mentioned in DisplayPort up to the 2.0 version.
  • Supports HPD-based link training.
  • Supports DPCD registers up to DisplayPort version 2.0 specification.
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW colour format.
  • Supports mainstream attribute (MSA) packets.
  • Supports following Secondary packets, Audio timestamp, Audio stream, Extension, Audio copy management, ISRC, VSC, Camera SDP 8 to 15, Info frame formats, VSC extension VESA, VSC extension CEA, Picture Parameter Set (PPS), Adaptive-Sync SDP
  • Supports Split SDP for both SST and MST mode.
  • Supports all audio formats which are mentioned in IEC 60958-1, IEC 60958-3, IEC 60958-4, IEC 61937-1, IEC 61937-3, CEA/CTA 861-F,861-G
  • Supports training pattern sequence (TPS2, TPS3, TPS4)
  • Supports descrambler as in DisplayPort specification.
  • Descrambler can be enabled or disabled dynamically.
  • Supports descrambler reset after every 512th symbol.
  • Supports Multi-Stream Transport (MST) operation.
  • Supports Advanced Link Power Management to reduce wake latency.
  • Supports GTC-based video timing synchronization.
  • Supports Display Stream De-Compression (DSC) up to version 1.2a
  • Supports high-bandwidth Digital Content Protection System up to version2.3 (HDCP v2.3)
  • Supports Horizontal Blanking Expansion
  • Supports RBR, HBR, HBR2, HBR3 and Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link.
  • Supports Panel Replay
  • Support Fully synthesizable
  • Support Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Deliverables

  • The DisplayPort Receiver interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
Request Datasheet