Description and Features
MIPI RFFE Verification IP provides an smart way to verify the MIPI RFFE bi-directional two-wire bus. The MIPI RFFE Verification IP is fully compliant with version 1.0,2.0,2.1 and 3.0 MIPI Alliance specification for RF Front-End Control Interface and provides the following features. MIPI RFFE Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env MIPI RFFE Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.

Features
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Full MIPI RFFE Master and Slave functionality.
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Operates as a Master, Slave, or both.
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Monitor, Detects and notifies the testbench of all protocol and timing errors.
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Supports all topologies as per the MIPI RFFE specification.
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Supports following frames. • Command Frame • Data/Address Frame • No Response Frame • Bus ownership transfer • Interrupt polling • Master write and read • Master context write and context read
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Various kind of Master and Slave errors generation. • Undefined command frame • Command frame with parity, length error • Address frame with parity error • Data frame with parity error • Read and Write of unused register • Read using the broadcast ID or a GSID • Various errors in Bus ownership transfer
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Glitch monitor and injection. • Support injection of glitch at all positions of SDATA and SCLK • Supports detection of glitches
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Supports interrupt summary and identification command sequence.
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Supports Master ownership handover.
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Support Master write and read sequence.
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Support Trigger and Extended trigger modes.
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Support Masked write command sequence.
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Support Silent Master initiated bus park.
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Support Interrupt capable slave.
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Support Synchronous read.
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Support Normal and Secondary operation mode.
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Support USID Programming Procedure 1,2 and 3.
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Support Group slave ID, Low power testing
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Support Timed Trigger and Mappable Trigger.
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Support Bus Clocked Condition.
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Supports device enumeration.
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Bus-accurate timing, Supports half speed.
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Callbacks in master, slave and monitor for variousevents.
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Status counters for various events in bus.
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Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Deliverables
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Complete regression suite containing all the MIPI RFFE testcases.
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Examples showing how to connect various components, and usage of Master, Slave and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes