Description and Features
The 200GBase-KR8/KR4/KR2 Ethernet Verification IP is compliant with IEEE 802.3bs specifications and verifies MAC-to-PHY layer interfaces of designs with a 200GBase-KR8/KR4/KR2 Ethernet interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. 200GBase-KR8/KR4/KR2 verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product. 200GBase-KR8/KR4/KR2 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and nonstandard verification env 200GBase-KR8/KR4/KR2 Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging

Features
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Supports 200GBase-KR8/KR4/KR2 interfaces as per the specifications defined in IEEE 802.3bs
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Supports scrambler
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Supports FEC
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Supports CDAUI_16
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Supports CDMII
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Supports backplane auto-negotation
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Supports CDR for serial protocols
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Supports MDIO slave and master model as per Clause 22 and Clause 45
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Supports Glitch insertion and detection
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Supports Pause frame generation and detection.
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Supports all types of 200GBase-KR8/KR4/KR2 TX and RX errors insertion/detection. • Oversize, undersize, inrange, out of range Packet size errors • Missing SPD/EPD/SFD framing errors • SFD on wrong lane • CRC Error • Lane skew insertion • Invalid /D/ and /K/ character injection • Variable preamble and IPG insertion • Invalid block code insertion • Sync bit corruption • FEC error injection • Scrambler error injection
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Comes with 200GBase-KR8/KR4/KR2 Tx BFM, 200GBase-KR8/KR4/KR2 Rx BFM, and 200GBase- KR8/KR4/KR2 PCS Monitor
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Supports MDIO slave and master model as per Clause 22 and Clause 45
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Monitor supports detection of all protocol violations.
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Built in coverage analysis.
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Callbacks in master and slave for various events
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Status counters for various events in bus
Deliverables
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Complete regression suite containing all the testcases.
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Examples showing how to connect variouscomponents, and usage of TXRX BFM and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes.