Description and Features
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP. With compatibility for PIPE 4.3 interface spec, this complies with PCIe Rev3 Base Specification. 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, all three are supported by the output data rate (serial), which has a 25Mhz input clock frequency. 2.5, 5, and 8 gigabits per second. A minimum of 10 Pads and a maximum clock speed of 500MHz are needed. Range of operating voltages: - 2.97V-3.63V, typical =3.3V; 0.99V-1.21V, usual = 1.1V;
Features
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Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
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Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
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Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
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Tunable receiver detection to detect worse case cables
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Beacon transmission and reception
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Support SSCG function to reduce EMI effects with tunable down-spread amplitude
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Selectable TX margining, TX de-emphasis and signal swing values
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Built-in-self-test with internal Loopback test option
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Programmable analog circuit parameter adjustment and internal test control
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Compliant with PCIe Rev3 base specification
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Silicon Proven in TSMC 40LP
Benefits
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Low Area
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Low Power
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Compliant with PCIe® 3.1, 2.1, 1.1, and PIPE specifications
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PCIe PHY functionality is fully verified
Applications
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Notebooks
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Smartphones
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Tablets
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Embedded mobile computing
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Ultraportable laptops
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Automotive
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Mobile multimedia
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Digital home
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Digital office
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Wireless connectivity
Deliverables
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Application Note / User Manual
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Behavior model, and protected RTL codes
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Protected Post layout netlist and Standard Delay Format (SDF)
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Synopsys library (LIB)
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Frame view (LEF)
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Metal GDS (GDSII)
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Test patterns and Test Documentation
