Description
The DDR2 component of a SOC or ASIC may be intelligently verified with the help of DDR2 Monitor. The DDR2 Monitor offers the following characteristics and complies fully with the DDR2 Standard Specification. DDR2 Monitor Verification IP comes with an optional Smart Visual Protocol Debugger, which is a GUI-based debugger to speed up debugging. DDR2 Monitor Verification IP is natively supported in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E, and non-standard verification environments.
Features
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Supports DDR2 memory devices from all leading vendors
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Quickly validates the implementation of the DDR2 standard
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Constantly monitors DDR2 behavior during simulation
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Checks for following • Check-points include Initialization rules, • State based rules, Active Command rules, • Read/Write Command rules etc.
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Support for full-timing as well as behavioral versions in one model
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Support for all timing delay ranges in one model: min, typical and max
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Built in coverage analysis
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Supports Callbacks, so that user can access the data observed by monitor.
Deliverables
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Complete regression suite containing all the DDR2 testcases.
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Examples showing how to connect and usage of Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes.
