The NVMe bi-directional bus may be verified using the NVMe Verification IP. The NVMe Verification IP offers the following functionalities and is completely compatible with the NVM-Express-1_4- 2019. 06.10-Ratified specification. SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E, and non-standard verification environments all natively support NVMe Verification IP. The optional Smart Visual Protocol Debugger for NVMe Verification IP is a GUI-based debugger that speeds up debugging.
UVM and Verilog APIs supplied, as well as C DPI exports.
Automated Error Injections at all layers
Supports Interrupt Mechanism
Supports Data Integrity as End to End Data Protection.
Supports Submission and completion queue management
Supports Controller Memory Buffer
Supports memory description as PRP/SGL description list
Supports Boot partitions operations
Supports Namespace subsystem
NVMe over PCIe • Supports complaint and optimized TLP packets. • Supports PIPE, PCS/PMA, and serdes interface • Full link speed and width negotiation up to 32 Lanes • Queuing for VCs with configurable depth • Configurable TC to VC queue mapping • User interface for direct TLP queuing and receipt • Checks all framing, LCRC, and lane rules • Check all DLLP fields and formatting • Interface to send / receive user defined DLLPs • Full LTSSM state machine • SERDES model with digital clock recovery • Supports Up configure, polarity inversion, and lane-to-lane skew • Supports for Conventional PCI Advanced Features • Supports PAM4 encoding scheme • Supports Gray coding and Tx Precoding • Supports Link management DLLP • Compliant with PIPE 5.2.1 Specification
NVMe Verification IP comes with complete test suite to test every feature of NVMe specification.
Supports UNH-IOL testing service
Functional coverage for complete NVMe features.
Callbacks in BFM’s and Monitor for various events.
Complete regression suite containing all the NVMe testcases to certify NVMe BFM's.
Examples showing how to connect various components, and usage of NVMe BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes