Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M PCI Express PCIe 2.0 Serdes PHY IP in 55ULP/65ULP

PCIe 2.0 Serdes PHY IP in 55ULP/65ULP

Description and Features

The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area (sub-0.30mm2), without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.

  • Compliant with PCIe2.0 specification
  • Standard PHY interface (PIPE) enables multiple IP sources for PCIe2.0 MAC layer
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Supports 16-bit or 32-bit parallel interface
  • 8b/10b encoder/decoder and error indication
  • Tunable Receiver detection to detect worse case cables
  • Beacon signal transmission and reception in PCIe mode
  • Supports SSC to reduce EMI effects with tunable down-spread amplitude
  • Selectable TX margining, Tx de-emphasis and signal swing values
  • Internal Loopback Test Capable
  • Allowable analog circuit parameter adjustment and internal test control
  • Built-in Self Test with embedded Jitter Injection
  • Output Jitter reduction with constant power technique
  • Automatic De-skew adjustment
  • Support Silicon Proven in TSMC 55ULP / 65ULP


  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behavior model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports