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Semiconductor IP Cores

T2M › PCI Express › PCIe 3.0 Serdes PHY IP in 12SF+/SF++

PCIe 3.0 Serdes PHY IP in 12SF+/SF++

Description

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area.

 

Features

  • Silicon Proven in SMIC 12SF+ with 0.8V and 1.8V power supply.

  • Compatible with PCIe base Specification

  • Support 32-bit/16-bit parallel interface

  • Support for PCIe3(8.0Gbps)

  • Backward compatible with 2.5Gbps and 5Gbps for

  • Full compatible with PIPE4.2 interface specification

  • Support 100MHz differential reference clock input/output (with SSC optionally)

  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA

  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm

  • Support programmable transmit amplitude and Deemphasis, Pre-shoot

  • Support Beacon signal generation and detection

  • Production test support is optimized through high coverage at-speed BIST and loopback

  • Integrated on-die termination resistors and IO Pads/Bumps

  • Embedded Primary & Secondary ESD Protection

Deliverables

  • Application Note / User Manual

  • Behavior model, and protected RTL codes

  • Protected Post layout netlist and

  • Standard Delay Format (SDF)

  • Synopsys library (LIB)

  • Frame view (LEF)

  • Metal GDS (GDSII)

  • Test patterns and Test Documentation

Benefits

  • Physical coding sublayer (PCS) block with PIPE interface

  • Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization

  • Spread-spectrum clocking (SRIS)

  • Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options

  • Multi-channel PHY macro with single clock and control core for higher density

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