A Universal Serial Bus (USB) transceiver is available for peripheral devices. The PHY complies with the USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI specifications. Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. The USB3.0 PHY IP ensures complete support for high-performance designs by including a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalisation circuit. The USB3 MAC layer is supported for multiple IP sources through the common PHY interface (PIPE). Internal test monitoring and allowed analogue circuit parameter tinkering Utilizing constant power, integrated Jitter Injection Output, and built-in Self-Test, jitter is minimised.
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Deliverables
Integrated Circuit Layout with Layer Mapping in GDS2
Views of Placement and Routing in LEF Format .
lib File Containing Timing and Power Characteristics
Verilog Behavioral Description for Functional Simulation
SDF Timing Constraints Applied to Circuit Netlist
Design Guidelines for Layout Implementation
Validation Reports for Layout Consistency and Rule Adherence
