Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M SerDes 12G Multiprotocol Serdes IP in 14SFP

12G Multiprotocol Serdes IP in 14SFP

Description and Features

The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. Silicon Proven in SMIC 28nm.


  • A universal SERDES IP that operation from 1Gbps to 12.5 Gbps
  • Compatible with PCIe/USB3/SATA base Specification
  • Support 40-bit/32-bit/20-bit/16-bit parallel interface
  • Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps)
  • Backward compatible with 2.5Gbps for PCIe
  • Backward compatible with 1.5Gbps, 3.0Gbps for SATA
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis  Support TX detect RX function in PCIe and USB3.0 Mode
  • Support LFPS signal generation and detection in USB Mode  Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in SMIC 28SF


  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports


  • TV / set-top box
  • Automotive
  • Medical appliance
  • Multimedia / Amusement Devices
  • Other consumer product