eUSB Verification IP provides an smart way to verify the eUSB component of a SOC or a ASIC. It provides backward compatibility support for earliers versions 1.0 and 2.0 of USB specifications. The USB Verification IP is fully compliant with standard Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification Rev.1.1 and USB 1.1/USB 2.0 Specification. eUSB VIP data transfer can be done at different speeds. Which intuitively involves high speed(480 Mbit/s), full speed(12 Mbit/s) or low speed(1.5Mbit/s). eUSB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env . eUSB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Compatible with Embedded USB2 (eUSB2)
Physical Layer Supplement to the USB Revision 2.0 Specification Rev.1.1.
Fully compliant to the USB2.0 layer architecture with the following features: • Supports high-speed, full-speed, and lowspeed operation. • High-speed: Low voltage differential signaling. • Low-speed/Full-speed: Single-ended digital low-voltage signaling. • Supports selected single speed configuration in native mode. • Supports USB2.0 operation based on repeater architecture. • Supports link power management LPM-L1 (L1) and Suspend (L2). • Supports register access protocol (RAP) for eUSB device or repeater configurations. • Fully compliant to USB2.0 base spec at the protocol layer. • Supports Host and Peripheral model.
Supports both transaction level (Setup, In, Out, Ping) and packet level (Token, Data, Handshake, SOF) transmission/reception.