› USB › USB 4.0 Device Controller IP
USB 4.0 Device Controller IP
Description and Features
The USB 4.0 Device IP core is latest development that enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhancements to the popular USB standard while offering backwards compatibility with billions of USB-enabled devices currently in the market. It is validated using FPGA prototype with industry standard PHYs.
Initial Versions :
A single upstream USBv4 port with no downstream port
One Enhanced SS Device (and/or possibly One Enhanced SS Hub)
Supports 20G USB4 (Gen 2x2) and optionally 40G (Gen 3x2).
Subsequent Versions :
Include Enhanced SS Hub
Include PCIe and the DP Functions.
Includes USB 3.2 Peripheral Controller.
Optional support USB Enhanced USB Hub.
Includes USB3 UP Adaptor.
Optional support for DP Out Adaptor.
Optional support for PCIe Up Adaptor
Includes DROM as part of its registers. Optional interface to an external DROM.
Supports USB4 Gen 2x2 (20 Gbps) and USB4 Gen 3x2 (40 Gbps) Links.
Optional support for thunderbolt Gen 2 (10.3125 Gbps) & Gen 3 (20.625 Gbps) rates.
Optional bypass mode to support native USB v3.2
Support for Alt Mode and Billboard class via USB2 controller.
System Master Interface : 64 / 128 bit AXI Interface
System Slave Interface : 32 / 64 AHB/AXI Slave Interface
USB v4 Phy Interface : 40 / 80 bit PIPE 5.1 SERDES I/F
Side band Channel PHY Interface : Serial I/F
USB 2 PHY Interface : UTMI / ULPI I I/F
USB 4.0 increases data rates up to a minimum of 20Gbps (40Gbps is also supported)
USB 4.0 Device is virtually identical in protocol and thus retaining backwards compatibility with older versions 3.2,3.0, 2.0
Supports PIPE and UTMI+ PHY interfaces
Architectural features reduce power consumption
Optimized Device controller IP designed to achieve power boost
Mass storage devices
Display and docking applications
Configurable RTL Code
HDL based test bench and behavioral models
Protocol checkers, bus watchers and performance monitors
Configurable synthesis shell
FPGA Platform for Pre-Tape-out Validation