Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M USB USB 2.0 PHY IP in 65LP

USB 2.0 PHY IP in 65LP

Description and Features

A complete physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP implements the High-Speed USB 2.0 transceiver, which can be used with hosts, devices, or OTG function controllers. The USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, comes after the UTMI+ level 3 specification. Several mixed-signal circuits combined can deliver 480Mbps of high-speed data transfer. The enhanced USB Battery Charging standards, which are designed for mobile and consumer product applications, are also supported by the USB2.0 PHY IP. The multiple production facilities and nodes that are present in the USB 2.0 PHY IP include TSMC 28HPC+, TSMC 40LP, TSMC 40LL, UMC 28HPC, UMC 40LP, UMC 55SP, UMC 55EF, SMIC 14SF+, SMIC 40LL, and SMIC 55LL. Performance and data throughput were unaffected by the tiny chip size and low power consumption of the USB2.0 PHY IP transceiver. The USB2.0 PHY IP offers a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to completely enable host and device functionality.

Features
  • Compliant with USB2.0 and USB1.1 specification

  • Compliant with UTMI Specification Version level 3.

  • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes

  • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip

  • 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS

  • Serializing for transmitting data stream and Deserializing for receiving data stream

  • USB Data Recovery and Clock Recovery on receiving

  • Integrated Bit Stuffing and NRZI encoding for Transmit

  • Integrated Bit Un-Stuffing and NRZI decoding for Receive

  • SYNC and EOP generation on transmit packets and detection on receive packets

  • Internal reference resistor that replaces the external reference resistor

  • Built in self test for production testing

  • Supports USB suspend state and remote wakeup

  • Supports detection of USB reset, suspend and resume signaling

  • Supports high speed identification and detection as defined by USB 2.0 Specification

  • Support high speed host disconnection detection

  • Silicon Proven in TSMC 28nm, TSMC 40nm, UMC 28nm, UMC 40nm, UMC 55nm, SMIC 14nm, SMIC 40nm, SMIC 55nm

  • Silicon Proven in TSMC 65LP.

Deliverables

  • Application Note / User Manual

  • Behavior model, and protected RTL codes

  • Protected Post layout netlist and Standard

  • Delay Format (SDF)

  • Frame view (LEF)

  • Metal GDS (GDSII)

  • Test patterns and Test Documentation