The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. Combo PHY IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT) This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers.
Deliverables
IC Layout Data with Layer Specifications in GDSII
LEF Views Illustrating Placement and Routing .
lib File Containing Timing and Power Models
Verilog Description of Circuit Behavior
Circuit Netlist Annotated with SDF Timing Constraints
Guidance and Recommendations for Layout Design
Reports on Layout Verification for Schematic and Rule Conformance
