The USB2.0 PHY IP is a complete physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0 transceiver is implemented by the USB2.0 IP and can be used with hosts, devices, or OTG function controllers. The UTMI+ level 3 specification is followed by the USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates. Using many mixed-signal circuits together, 480Mbps of high-speed data can be transmitted. The USB2.0 PHY IP also supports the expanded USB Battery Charging standards, which are intended for mobile and consumer product applications. The USB2.0 PHY IP transceiver's small chip size and low power consumption did not come at the expense of performance or data throughput. In order to provide complete support for host and device functionality, the USB2.0 PHY IP includes a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit.
Deliverables
Physical Layout Representation with Layer Mapping in GDSII
Representation of Placement and Routing Topology in .LEF
Liberty Format Repository for Timing and Power Models
Functional Simulation Model in Verilog Syntax
SDF Timing Specifications Integrated into Circuit Netlist
Guidelines for Successful Layout Implementation and Compliance
Verification Reports Confirming Layout Schematic and Rule Conformance
