JESD204 CYCLIC FEC core is compliant with JESD204C version specification.Through its compatibility, it provides a simple interface to a wide range of lowcost devices. JESD204 CYCLIC FEC IIP is proven in FPGA environment.The host interface of the JESD204 CYCLIC FEC can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXILite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol. JESD204 CYCLIC FEC IIP is supported natively in Verilog and VHDL
Compliant with JESD204 specification JESD204C.
Supports Full JESD204C FEC functionality.
This FEC(Forward Error correction) methodology implements the (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661).
Supports FEC of 26 bits parity bits.
Supports Error correct up to 9-bit burst error.
Supports the pipelined mechanism for the error correction.
FEC has a minimum latency of 58 blocks in the detection and correction of a bit error in the first scrambled data bit of a multiblock.
Deliverables
The JESD204 CYCLIC FEC interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases.
