USB 2.0 PHY IP in 28HPC

Description

The USB 2.0 PHY IP Core offers a complete physical layer (PHY) solution for high performance and low power. It implements a High-Speed USB 2.0 transceiver compatible with host, device, and On-The-Go (OTG) controllers. Supporting UTMI+ level 3, the PHY also offers backward compatibility with Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates.

Combined with mixed-signal circuits, it delivers 480 Mbps of high-speed data transfer. Additionally, the USB 2.0 PHY IP supports USB Battery Charging specifications, targeting mobile and consumer products. The transceiver prioritizes low power consumption and minimal die area while maintaining performance and data throughput.

For comprehensive host and device support, it integrates a full on-chip solution with ESD protection, an internal PLL clock generation block, and a resistor termination calibration circuit.

calibration circuit.

Features

• Compliant with USB2.0 and USB1.1 specification
• Compliant with UTMI Specification Version level 3.
• Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
• All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
• 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS
• Serializing for transmitting data stream and Deserializing for receiving data stream
• USB Data Recovery and Clock Recovery on receiving
• Integrated Bit Stuffing and NRZI encoding for Transmit
• Integrated Bit Un-Stuffing and NRZI decoding for Receive
• SYNC and EOP generation on transmit packets and detection on receive packets
• Internal reference resistor that replaces the external reference resistor
• Built in self test for production testing
• Supports USB suspend state and remote wakeup
• Supports detection of USB reset, suspend and resume signaling
• Supports high speed identification and detection as defined by USB 2.0 Specification
• Support high speed host disconnection detection
• Silicon Proven in UMC 28HPC

Deliverables

• GDSII Format with Detailed Layer Allocation

• Views of Placement and Routing in .LEF Format

• Standard Cell Library with Extensive Timing and Power Characterization

• Behavioral Model Expressed in Verilog Language

• Netlist Including Timing Annotations in SDF

• Recommendations for Effective Layout Design and Execution

• Validation Reports Ensuring Layout Adherence to Schematic and Rules