Description and Features
USB 4.0 Verification IP provides a smart way to verify the USB 4.0 component of a SOC or an ASIC. The USB 4.0 Verification IP is fully compliant with standard USB Specification 4.0. The USB 4.0 VIP can be readily customized and optimized for a wide range of specific system applications. USB 4.0 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env. USB 4.0 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
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Compliant with USB4.0 Specification
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Supports USB4.0 Gen2 and Gen3 Operation
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Supports constrained randomization of protocol attributes
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Supports all types of error injection and detection
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Supports error injection in all the layers of USB 4.0
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Supports Dual Lane
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Supports Lane margining and Lane de-skew buffer
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Supports Side band channels
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Supports SERIAL, PIPE and SERDES Interface
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Configurable PIPE Interface width 8, 16 or 32 bits
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Configurable SERDES Interface width 32, 40, 64 and 80 bits
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Supports Enumeration process to enumerate hub/device
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Supports 64/66B Encoding and Decoding for Gen2
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Supports 128/132B Encoding and Decoding for Gen3
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Supports Scrambler and Descrambler
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Supports RS-Forward Error Correction (FEC)
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Supports Clock compensation
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Supports Spread spectrum clocking
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Supports jitter
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Supports Side band register space
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Supports Configuration register space
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Supports Lane adapter, Protocol adapter and Control adapter operations
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Supports Lane initialization process
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Supports Low power state
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Supports Lane bonding mechanism
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Supports Error detection and Recovery mechanism
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Supports USB4 Link Equalization TxFFE handshake.
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Supports all the Side Band Channel transactions
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Supports Sleep and Wake mechanism with respect to the tunneled protocols
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Supports Hot plug detection and Disconnect detection
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Supports SKIP Insertion and Removal
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Supports Time Sync Notification Ordered Set (TSNOS)
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Supports following Protocol tunneling, • USB3 tunneling • Display port tunneling • PCIE tunneling
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Supports all the Transport layer packets
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Supports HEC, ECC and CRC
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Supports Path Setup & Path Tear-Down mechanism
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Supports all the Control packets
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Supports all the Notification events
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Supports Time Synchronization
Deliverables
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Complete regression suite containing all the USB 4.0 testcases.
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Examples showing how to connect various components, and usage of BFM and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes.