Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M Ethernet Ethernet 25G PCS IP

Ethernet 25G PCS IP

Description and Features

Ethernet 25G PCS IP Core adheres to the IEEE Standard 802.3.2018. Its Ethernet compatibility enables a straightforward interface to be used with a variety of inexpensive devices. Ethernet 25G PCS IP has been validated in an FPGA setting. Additionally, it can handle a wide range of host bus interfaces, including AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone, and custom buses, making it simple to integrate into any design architecture.

 

Ethernet-25G-PCS-silicon-proven-ip-provider-in-china 

Features
  • Supports IEEE Standard 802.3.2018 Clause 107
  • Supports 25G Base R
  • Supports 25G Base KR
  • Supports 64b/66b encoding and decoding for transmit and receive path
  • Supports data scrambling on the transmit path and descrambling on the receive path
  • Supports gearbox for various XSBI data width
  • Supports Block synchronization
  • Supports Bit Error Rate monitoring
  • Supports receiver Link fault status detection
  • Supports Loopback functionality
  • Supports IEEE 802.3az Energy Efficient Ethernet
  • Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
  • Supports PCS to Serdes Interface for all the data widths
  • Support RS FEC as per clause 108 of IEEE Standard 802.3.2018
  • Optional Support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
  • Optional support for Test pattern generation and error checkers
  • Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
  • Optional support for link training as per clause 72 of IEEE Standard 802.3.2018
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

  • The Ethernet interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes