Description and Features
Ethernet 25G PCS IP Core adheres to the IEEE Standard 802.3.2018. Its Ethernet compatibility enables a straightforward interface to be used with a variety of inexpensive devices. Ethernet 25G PCS IP has been validated in an FPGA setting. Additionally, it can handle a wide range of host bus interfaces, including AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone, and custom buses, making it simple to integrate into any design architecture.
Features
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Supports IEEE Standard 802.3.2018 Clause 107
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Supports 25G Base R
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Supports 25G Base KR
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Supports 64b/66b encoding and decoding for transmit and receive path
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Supports data scrambling on the transmit path and descrambling on the receive path
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Supports gearbox for various XSBI data width
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Supports Block synchronization
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Supports Bit Error Rate monitoring
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Supports receiver Link fault status detection
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Supports Loopback functionality
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Supports IEEE 802.3az Energy Efficient Ethernet
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Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
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Supports PCS to Serdes Interface for all the data widths
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Support RS FEC as per clause 108 of IEEE Standard 802.3.2018
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Optional Support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
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Optional support for Test pattern generation and error checkers
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Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
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Optional support for link training as per clause 72 of IEEE Standard 802.3.2018
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Benefits
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Single Site license option is provided to companies designing in a single site.
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Multi Sites license option is provided to companies designing in multiple sites.
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Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
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Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
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The Ethernet interface is available in Source and netlist products.
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The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes